Altera_Forum
Honored Contributor
8 years agoUnable to create FPGA configuration file using "hello_world" example
hi,
I have been trying to compile this example for the a10gx board, but always get the following:
aoc -v --board a10gx device/hello_world.cl -o bin/hello_world.aocx
aoc: Environment checks are completed successfully.
You are now compiling the full flow!!
aoc: Selected target board a10gx
aoc: Running OpenCL parser....
aoc: OpenCL parser completed successfully.
aoc: Compiling....
aoc: Linking with IP library ...
aoc: First stage compilation completed successfully.
Error: Compiler Error, not able to generate hardware
This is the error I got when checking the "quartus_sh_compile.log" file:
Error (15653): The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design.
Error (15744): In atom 'board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts.twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_sd.inst_twentynm_hssi_pma_rx_sd'
Error (15744): The settings must match one or more of these conditions:
Error (15744): ( sup_mode == ENGINEERING_MODE ) OR ( prot_mode != PCIE_GEN3_RX ) OR ( sd_output_off == CLK_DIVRX_14 )
Error (15744): But the following assignments violate the above conditions:
Error (15744): sup_mode = USER_MODE
Error (15744): prot_mode = PCIE_GEN3_RX
Error (15744): sd_output_off = CLK_DIVRX_6
Error (18590): The imported netlist contains settings that are not supported by the current version of the software. Import using the --timing_analysis_mode option, which ignores the errors and allows Timing Analysis to be run.
Error: design::import_design -file base.qdb -overwrite failed!
Error (23031): Evaluation of Tcl script /opt/cad/altera/altera-16.1/quartus/common/tcl/internal/qatm_import_design.tcl unsuccessful
Error: Quartus Prime Compiler Database Interface was unsuccessful. 11 errors, 0 warnings
Error: Peak virtual memory: 4517 megabytes
Error: Processing ended: Tue Mar 21 18:57:05 2017
Error: Elapsed time: 00:18:24
Error: Total CPU time (on all processors): 00:18:07
...
Error (23031): Evaluation of Tcl script import_compile.tcl unsuccessful
Error: Quartus Prime Compiler Database Interface was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 1189 megabytes
Error: Processing ended: Tue Mar 21 18:57:07 2017
Error: Elapsed time: 00:18:28
Error: Total CPU time (on all processors): 00:18:11
Also I checked potential sources of error such as when using the tool through ssh, or problems due to localization settings. But besides that, I don't understand the tool suggestion:
The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design.
My compiler is:
aocl version
aocl 16.1.0.196 (Intel(R) FPGA SDK for OpenCL(TM), Version 16.1.0 Build 196, Copyright (C) 2016 Intel Corporation)
aoc --version
Intel(R) FPGA SDK for OpenCL(TM), 64-Bit Offline Compiler
Version 16.1.0 Build 196
Copyright (C) 2016 Intel Corporation
How could solve this? Any hint would be greatly appreciated!