Unable to assign AltPLL to PLL_L2 in Stratix III (EP3SE260) using Quartus II 9.1

Initially, I assign input clock of PLL to pin_T33(clk1p) or pin_V31(clk0p) and first output clock of PLL to pin_T29(PLL_L2_FB_CLKOUT0p pin) & compile the project. I found out the PLL is assigned to PLL_L3 in the filter report although I have assigned the PLL to PLL_L2 according to Stratix III device pin-out file.

After that, I tried to unassign the input & output clock of this PLL. I add a location assignment for this PLL instance to PLL_L2. But, I can't compile the project successfully. It maybe due to the wrong selection actual PLL instance name? Do you know which filter I should select in node finder so that it can list the actual PLL instance name?

Thanks