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Altera_Forum
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16 years ago

Unable to assign AltPLL to PLL_L2 in Stratix III (EP3SE260) using Quartus II 9.1

I have a PLL with 4 different frequency outputs clock. I assign this PLL to PLL_L2 & one of this PLL output clocks is assigned to PLL_L2_FB_CLKOUT0p pin. After compiling the project, it automatically...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Quartus is possibly assigning the PLL location due to the clock input connection. You can add a location assignment in the Quartus Assignment Editor. You have to browse the design hierarchy and locate the actual PLL instance name, like in the below example 

set_location_assignment PLL_2 -to "ad9259:adu_control_inst|altpll:ADCLK|pll32_altpll1:auto_generated"