UART in Verilog, testing in Modelsim/Quartus

You can/should defer debugging with SignalTap until you really run into trouble.

The approach is to first simulate. With the internal simulator (before QII 10.0) it was easy, you just copied the waveform of the TxD output, as generated by the simulation, onto the RxD input waveform and then ran a second simulation to see whether reception runs OK. I don't have experience with ModelSim (yet ...) but there's another trick you can use: connect the TxD output back into the rxd pin of the UART function, so you don't need to hassle around with copying waveforms or generating a complicated testbench.

Maybe add some logic to switch either to the external RxD pin or to the internal loopback of TxD.