UART core simulation

Hi @BAdam1,

Thank you for posting in Intel community forum and hope this message find you well.
As per discussion and some investigation, the RTL code structure of the testbenches are incorrect as not accordingly to the recommended structure.
To write a testbenches code for the avalon, would recommend to start the user guide here, which will be a great starting point. (e.g. below example can also be a great references)

Process to write a testbench to validate the behavior of the IP can be lengthy sometime.
Perhaps would suggest to system console which is a much easier, for that the example here would be a good starting point. (i.e. may refer to the 'Introduction to FPGA Simulation and Debug' workshop)

Thank you

Warm regards.
BB