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Altera_Forum's avatar
Altera_Forum
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16 years ago

Two stage synthsis

Hi

I have a design which I've ported over from Xilinx. One thing that I havent been able to achieve in Quartus is being able to segment the design into two parts, synthesize them seperately and then link them together in the PAR.

What I have is two sections, Top and Bottom with top instantiating bottom. I then have a file called Bottom_blackbox which top references when being synthesized, therefore not bringing up errors that lower sections cant be found. This strategy works for Xilinx ISE, Synplify (whether targetting Xilinx or Altera)

Quartus (scripting) reports that the blackbox pins have no underlying connection and therefore get set to GND. Subsequently in PAR it reports again that the pins of the device are set the GND (due to optimization and the fact that the Bottom didnt get linked in)

Is there something else I need to do? My blackbox architecture has the following

attribute syn_black_box : boolean;

attribute syn_black_box of default : architecture is true;

attribute black_box : boolean;

attribute black_box of default : architecture is true;

I'm not sure if both are needed, but I had found a Altera example that didnt include the "syn_"

Possibly another option would to be use partitioning?? I would like to get the original strategy working first if it is possible before moving onto partitioning (if that was applicable).

Any suggestions would be appreciated

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I don't fully get how it's done in ISE(and Synplify it's straightforward since it's just synthesis), but you want to use Incremental Compilation. Worth going through the documentation, but it's basically all handled in Quartus, rather than HDL assignments, so you don't have to go in and modify HDL when you're really just trying to modify what is placed and routed.

    Assuming you're using Quartus Integrated Synthesis, do a Processing -> Start -> Analysis & Elaboration in a project that has everything in it. This is just a quick pass to get a hierarchy build up. Go into the Hierarchy Browser, find the hierarchy you want, and right-click Create Partition. To view the partition window go to Assignments -> Design Partition Window.

    Two things of note:

    1) You're top-level hierarchy(which is always a partition) can't be Empty. So there's no way to place-and-route the lower-level.

    2) If you make a hierarchy/partition Empty, all the hierarchies below it are automatically empty. (This may change in the future).

    I haven't seen that be a problem, as most setups have parallel hierarchies that the user wants to create partitions out of(they don't have to be the same depth, but they don't have one inside another).

    If you really want to compile a lower level first, I would recommend changing the hierarchy, but one thing I've done to emulate that flow is to:

    1) Create a partition on the highest hierarchy leaves that are not directly in the path of the hierarchy I want. Basically the largest hierarchies that don't contain the one in question. I also put a partition on the one I want.

    2) Set all the adjacent partitions to emtpy, so they basically disappear and my compile is mainly just fitting the low-level partition I want it to work on.

    3) When it's done and if it's what I want, I delete the all the partitions except for the one on that hierarchy, so basically everything else is flat. I set that partition to Post-Fit Placement and the rerun the fitter, so everything else it fit around it.

    You could also do a bottom-up approach, where you do a compile on the lower-level one first and then export a .qxp which gets imported into your main project. Personally, the flow I described is generally easier(even if it sounds complicated in this post, it's usually only a minute or two of work)