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I understand that anyone without detailed knowledge probably won't be able to help me, but as you said, maybe i get lucky to find someone that has worked before with that board.
I also asked helped for T.I., i'm trying all the possible ways to solve it, but through my research and their feedback, what i'am attempting to do has never been tried.
My intention on asking Altera's help is to find a direction on how to replace, if possible, a PLL in the Altera stratix IV FPGA.
Thanks for your advices and time.
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I'm guessing that with ADCs and DACs the designs are using LVDS serdes, which are usually built with the PLLs internal to the IP (which is just a logical partition, the PLLs are separate on the chip). If that's what's going on then you could rebuild the LVDS serdes IP cores to use an external PLL, then you may be able to share PLLs between the ADC (LVDS Rx) and DAC (LVDS Tx) interfaces. But it will most likely be on you to dig in, do the research, and make the changes.
As ted said, post back here with specific questions after you dive into the designs a little deeper.
Bob
Honored Contributor
