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Altera_Forum's avatar
Altera_Forum
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15 years ago

Trying to integrate verilog file into vhdl project

Hi I'm sure this question has been asked before but I can't seem to find an answer to it. I am trying to use a verilog file in a vhdl project like this: u1 : entity work.sdram port ma...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You have to treat the verilog like a black box. so you will need a component declaration else the VHDL has no knowledge of the existance of the Verilog, and hence throws the error. This way you can instantial verilog or AHDL entities from VHDL.