Trying to get State Machine to Stop Glitching

I began to rewrite the code to get rid of some of the unnecessary factors mentioned above and developed this code bellow. Even after doing all that my code still glitches.

https://www.alteraforum.com/forum/attachment.php?attachmentid=11099

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_textio.all;

use IEEE.std_logic_unsigned.all;

library STD;

use STD.textio;

ENTITY state_machine IS

generic(txNum:integer:=5);

PORT(

clk : IN STD_LOGIC;

reset : IN STD_LOGIC;

txen_1 : out std_logic;

txen_2 : out std_logic;

txen_3 : out std_logic;

txen_4 : out std_logic;

txen_5 : out std_logic;

rxen_1 : out std_logic;

rxen_2 : out std_logic;

rxen_3 : out std_logic;

rxen_4 : out std_logic;

rxen_5 : out std_logic);

END state_machine;

ARCHITECTURE a OF state_machine IS

constant s0:STD_LOGIC_vector(2 downto 0):="000";

constant s1:STD_LOGIC_vector(2 downto 0):="001";

constant s2:STD_LOGIC_vector(2 downto 0):="010";

constant s3:STD_LOGIC_vector(2 downto 0):="011";

constant s4:STD_LOGIC_vector(2 downto 0):="100";

constant s5:STD_LOGIC_vector(2 downto 0):="101";

signal state: STD_LOGIC_vector(2 downto 0):=s0;

signal cnt:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";

BEGIN

process(clk)

begin

if(rising_edge(clk))then

cnt<=cnt+1;

end if;

end process;

PROCESS (clk,reset)

BEGIN

IF reset = '1' THEN

state <= s0;

ELSIF (rising_edge(clk)) THEN

CASE state IS

WHEN s0=>

state <= s1;

WHEN s1=>

if(cnt="1111")then

if(txNum=1)then

state <= s1;

else

state <= s2;

end if;

else

state <= s1;

end if;

WHEN s2=>

if(cnt="1111")then

if(txNum=2)then

state <= s1;

else

state <= s3;

end if;

else

state <= s2;

end if;

WHEN s3=>

if(cnt="1111")then

if(txNum=3)then

state <= s1;

else

state <= s4;

end if;

else

state <= s3;

end if;

WHEN s4=>

if(cnt="1111")then

if(txNum=4)then

state <= s1;

else

state <= s5;

end if;

else

state <= s4;

end if;

WHEN s5=>

if(cnt="1111")then

state <= s1;

end if;

when others=>

state<=s1;

END CASE;

END IF;

END PROCESS;

PROCESS (state)

BEGIN

rxen_1<='1';

rxen_2<='1';

rxen_3<='1';

rxen_4<='1';

rxen_5<='1';

CASE state IS

WHEN s0 =>

txen_1<='0';

txen_2<='0';

txen_3<='0';

txen_4<='0';

txen_5<='0';

WHEN s1 =>

txen_1<='1';

txen_2<='0';

txen_3<='0';

txen_4<='0';

txen_5<='0';

WHEN s2 =>

txen_1<='0';

txen_2<='1';

txen_3<='0';

txen_4<='0';

txen_5<='0';

when s3=>

txen_1<='0';

txen_2<='0';

txen_3<='1';

txen_4<='0';

txen_5<='0';

when s4=>

txen_1<='0';

txen_2<='0';

txen_3<='0';

txen_4<='1';

txen_5<='0';

when s5=>

txen_1<='0';

txen_2<='0';

txen_3<='0';

txen_4<='0';

txen_5<='1';

when others=>

txen_1<='1';

txen_2<='0';

txen_3<='0';

txen_4<='0';

txen_5<='0';

END CASE;

END PROCESS;

END a;