Trying to get State Machine to Stop Glitching

There are some issues with this code:

The rxen_x and txen_x signals are not all assigned in every state - this is going to form latches that could cause odd timing problems,. With an asynchronous process ALL signals must be assigned in ALL starts to prevent the formation of latches.The easy way around this is to assign each signal a default (including next_s) before the case statement. This gives each signal a value should it not be assigned somewhere else (it also must be an explicit value, not itself - that is a latch).

Where does clkrx come from?

Why is clkout assigned from clkrx based on p? p is true after the first clock. Routing clocks like this is a really bad idea. Apart from latching the clock (which is a bad idea), when you simulate the design, clkout is going to be 1 delta behind clkrx, which is going to do some odd things in your simulation and you probably wont have a clue whats going on. Moral of the story - use the same clock everywhere, dont use assigned versions.