Trying to get State Machine to Stop Glitching

I'm not sure what's causing the problem, but you have a bug in your counter code:

SIGNAL cnt : INTEGER RANGE 0 TO 16 := 0;
PROCESS (clkrx)
BEGIN
  IF (rising_edge(clkrx)) THEN
    IF (cnt = 0) THEN
      current_s <= next_s;
      cnt <= cnt + 1;
      p <= true;
    ELSIF (cnt = 16) THEN
      current_s <= next_s;
      cnt <= cnt + 2;
    ELSE
      cnt <= cnt + 1;
    END IF;
  END IF;
END PROCESS;

You are defining a range from 0 to 16, but when you reach 16 you still increase the counter, getting out of range. This kind of behaviour is undefined in VHDL (and will cause an error in a simulator). I'm not sure what Quartus synthesizes in this case, but it's quite possible that it's an +1 adder that works fine with numbers from 0 to 16 and gives strange results for other values.

Try this instead:

SIGNAL cnt : INTEGER RANGE 0 TO 15 := 0;
PROCESS (clkrx)
BEGIN
  IF (rising_edge(clkrx)) THEN
    IF (cnt = 0) THEN
      current_s <= next_s;
      cnt <= cnt + 1;
      p <= true;
    ELSIF (cnt = 15) THEN
      cnt <= 0;
    ELSE
      cnt <= cnt + 1;
    END IF;
  END IF;
END PROCESS;

It will synthesize as a regular adder, and uses one bit less.

Which clock frequency are you using for this design? Did you constrain your project for Timequest?