Trying to generate a signal.

Thanks a lot for you answers! Unfortunately, they did not worked for me. I have the following problems:

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Tricky's answer is certainly the most elegant way to do exactly what you asked.

If you wanted to test all possibilities, another way would be to use an unsigned 8-bit signal and just increment it by one each clock cycle. first is the upper 4-bits and second is the lower 4-bits. You could even get rid of first and second and just write:

    signal counter : unsigned(7 downto 0) := (others => '0');
process
begin
    wait for rising_edge(clk);
    counter <= counter + 1;
    a3 <= counter(7);
    a2 <= counter(6);
   ...
    b3 <= counter(3);
    ...
    b0 <= counter(0);
end process;

If you're allowed to make a and b arrays (maybe call them first and second), it would get even simpler and then easily scales to other size operands.

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Instead of the loops, I have copied this, but then an error shows up:

"rising_edge type specified in Qualified Expression must match time type that is implied for expression by context"

And I don't exactly know how to solve it, I have googled it but no one of the answers worked :(

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Thats because the loop that occurs on the clock edges (and it will be both falling and rising edge, because you didnt put an edge condition in there) completes on every loop. Because signals only take the last thing assigned to them, they take the last assignment, which is 9.

You need a wait in the loop so that it increments on every clock. Something like this:

use ieee.numeric_std.all;
process   -- note - no sensitivity list
  variable first, second : unsigned(3 downto 0);
begin
  for i in 0 to 9 loop
    second := to_unsigned(i, 4);
    
    b3 <= second(3);
    b2 <= second(2);
    b1 <= second(1);
    b0 <= second(0);
    for j in 0 to 9 loop
      first := to_unsigned(j, 4);
      a3 <= first(3);
      a2 <= first(2);
      a1 <= first(1);
      a0 <= first(0);
      wait until rising_edge(clk);
    end loop;
  end loop;
  wait;
end process;

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I tyied this one as well, and the problem is:

"Process statement must contain only one wait statement"

It works if I take it out of the loops, but the result is the same, in the simulation it only works with 9*9

I find the clock really logic, I mean, I realized that for sure I need one, but I still not knowing how to use it. Anyway I think I am closer to the answer :)