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Andy-1's avatar
Andy-1
Icon for New Contributor rankNew Contributor
1 year ago

Trying to assign I/O pins for LVDS on Cyclone 10 LP

I wondered if anyone could point me in the right direction on how to implement LVDS using the Quartus Prime Lite software. I have read documentation from both Altera and Intel on how to setup LVDS an...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,
to implement LVDS I/O according to Cyclone 10 specifications, VCCIO of 2.5 V is required for the respective banks.

I don't know if the intended pin is dedicated LVDS I/O. For slower LVDS speed (a few 100 MBPS), it's possible to use single ended I/O as emulated LVDS with resistor network to set the output level, also for 3.3V VCCIO. But LVDS RX is only available on dedicated LVDS pin pairs.

Regards
Frank