trouble with Quartus II error

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i write a testbench for a decoder but when i compile this file in quartus,this error comes out.

error: can't synthesize current design -- top partition does not contain any logic

but the same design files can be compiled in modelsim successfully.

who can tell me why? how to solve it?

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Hi,

did you try to synthesize the testbench ? The testbench has no inputs or outputs. I expect

that Quartus will remove all your logic, because no output depends on an input. A Testbench is only used for simulation.

Kind regards

GPK

--- Quote Start ---

Hi,

did you try to synthesize the testbench ? The testbench has no inputs or outputs. I expect

that Quartus will remove all your logic, because no output depends on an input. A Testbench is only used for simulation.

Kind regards

GPK

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thank you very much! now i knows.