Altera_Forum
Honored Contributor
13 years agoTrouble with coding a clock in verilog -> Error (10170)
I everything inside the always @ totally different and it compiled without errors but it definitely didn't do what I wanted it to. It counted the seconds fine but everything else was whacky so I started over. Any tips or suggestions on how I can make the errors go away and I can compile this?
module clock(set,onehertz,hour,minute,ampmset,hr_ten,hr_one,min_ten,min_one,sec_ten,sec_one,am_pm);
input onehertz,hour,minute,ampmset,set; //SW0 to set, KEY3 for hours, KEY2 for Minutes, KEY1 for AM or PM
output hr_ten,hr_one,min_ten,min_one,sec_ten,sec_one;
output am_pm;
reg hourtens,hourones,mintens,minones,sectens,secones;
reg ampm;
always @ (posedge onehertz) begin
if (set == 0) begin
secones <= secones+4'H1;
if ( secones > 4'H9 && sectens < 4'H6 ) begin
secones <= 4'H0;
sectens <= sectens+4'H1;
end else begin
sectens <= 4'H0;
minones <= minones+4'H1;
end else if ( minones > 4'H9 && mintens < 4'H6 ) begin //Line 18, first error
minones <= 4'H0;
mintens <= mintens+4'H1;
end else begin
mintens <= 4'H0;
hourones <= hourones+4'H1;
end else if ( hourones > 4'H9 && hourtens == 4'H0 ) begin //Line 24, second error
hourones <= 4'H0;
hourtens <= hourtens+4'H1;
end else if ( hourtens > 4'H1 && hourtens == 4'H2) begin
hourtens <= 4'H0;
if (ampm == 7'B0001100) begin
ampm <= 7'B0001000;
end else begin
ampm <= 7'B0001100;
end
end
end
if (set == 1) begin
if (hour == 1) begin
hourones <= hourones+4'H1;
if ( hourones > 4'H9 && hourtens == 4'H0) begin
hourones <= 4'H0;
hourtens <= hourtens+4'H1;
end else if ( hourtens == 4'H1 ) begin
hourtens <= 4'H0;
end
end
if (minute == 1) begin
minones <= minones+4'H1;
if ( minones > 4'H9 && mintens > 4'H5) begin
minones <= 4'H0;
mintens <= mintens+1;
end else if ( mintens > 4'H5 ) begin
mintens <= 4'H0;
end
end
if (ampmset == 1) begin
if (ampm == 7'B0001100) begin
ampm <= 7'B0001000;
end else begin
ampm <= 7'B0001100;
end
end
end
end
assign hr_ten = {hourtens};
assign hr_one = {hourones};
assign min_ten = {mintens};
assign min_one = {minones};
assign sec_ten = {sectens};
assign sec_one = {secones};
assign am_pm = {ampm};
endmodule Error (10170): Verilog HDL syntax error at clock.v(18) near text "else"; expecting "end" Error (10170): Verilog HDL syntax error at clock.v(24) near text "else"; expecting "end"