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Ok, here's the thing. I'm instantiating 3 components in the top level HDL, whose entity contains the avalon specific signals.
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I'm assuming you mean the top level SOPC system here, not the top level of the design (verilog/VHDL file)
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I map those signals onto few components. Now, when i try creating a IP out of that entity, the system generation etc. works fine, so does the programmer, but these top level entity's port signals appear on the pin assignment, "unassigned".
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I'm grasping at straws here, but one thing I saw in the past if you ever changed a component, you needed to remove and re-add it into the SOPC system. Otherwise, it would sometimes not get the signals assign correctly:
IE: If you originally generated the component, then you modified it (Especially if you changed any component IO's, if you didn't remove it from the SOPC system sometimes it wouldn't pick up the pin changes. The System would build but then you would get errors similar to this.
To correct it, all you need to do is remove the component from the SOPC system, then add it back in, and re-connect it before generating.
Hope this helps. If not, it might be helpful to have a screen shot of the system and the component pin setup.
Pete
Honored Contributor
