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I'm assuming you mean the top level SOPC system here, not the top level of the design (verilog/VHDL file)
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It is the top level of the design and not SOPC. and I'm not changing anything in the design file once the IP is created.
here's the screen shot of the entity of my top-level-design file. I'm trying to create this into a component IP in sopc builder by mapping it onto avalon slave.
http://www.kiranchandran.info/wp-content/uploads/2007/09/top-level-design.jpg (
http://www.kiranchandran.info/wp-content/uploads/2007/09/top-level-design.jpg)
and this is the sopc builder screen shot, my IP is surround_main.
http://www.kiranchandran.info/wp-content/uploads/2007/09/sopc.jpg (
http://www.kiranchandran.info/wp-content/uploads/2007/09/sopc.jpg)
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