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Altera_Forum's avatar
Altera_Forum
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14 years ago

Tri-state fanout converted to OR gate

Hi,

I'm writing Verilog code for an I2C expander with bidirectional 16-bit output.

If I need to read the status of the pins into a register, which means I the tr-state output pins are connected to a reg variable (along with the output pins), I get the below mentioned warning from Quartus.

Warning: Converted the fan-out from the tri-state buffer "i2c_expander_v2:i2c1|register_logic_v2:reg1|bidir_io:gpio15|io" to the node "i2c_expander_v2:i2c1|register_logic_v2:reg1|input_reg2[7]" into an OR gate

This occurs for all the 16-bits.

The device is Max II CPLD.

Any help how I go about this?

Ram

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    My bidirectional primitive is

    module bidir_io (

    input wire in,

    input wire oe,

    output out,

    inout wire io

    );

    assign io = oe ? in : 1'bz;

    assign out = io;

    endmodule

    I only use the 'out' to sense any changes to 'io' pin. So I'm not sure why the error points to 'io'.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The tri-state logic is burried in the I/O so it's not possible to assign a tristate signal directly to another signal. If you take a look at a diagram of the I/O logic of the FPGA this will become more clear.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    So if I need to read in the state of the bidirectional line, how do I do it without connecting anything to it?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Take a look at the design examples page on www.altera.com and search for "tristate". You'll find examples of what you are attempting to do.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thank you all.. I understood the issue after reading the above mentioned Altera doc link.

    Thanks

    Ram