Forum Discussion
Altera_Forum
Honored Contributor
8 years agoOK that makes sense.
Yea, converting from Quartus 9 -- MAX-II -- schematic to Quartus 16 -- MAX-10 -- Verilog, is not necessarily an easy step. I was wanting to keep as much schematic as I could for now, until I had more time to learn Verilog. Hopefully, the only issues I might have right now is the alt_IO portions. Once I get them converted to Verilog, we'll see how the rest compiles and works. Have a good weekend. Keith