Altera_Forum
Honored Contributor
Honored Contributortree structure
hii pls give an idea to implement a verilog code to construct a tree structure.Also an array reusing idea.because we need to reduce the array size each time.
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Altera_ForumHonored Contributor
Honored ContributorThis is far too few information.
What exactly do you need? Do you want to create a Top-Entity which holds one or more Objects of your Verilog-Code? I think for beginners it would be a good start to create a Symbol-File of your code and place it in a Schematic-File (*.bdf). Then you can actually "see" what you have programmed. What array? How do you want to reduce the array size? Hmmm, if I ask my crystal-ball I think you want to create some instances of a Verilog-Thingy holding an array, and every instance should hold an array of different size. If this is the case try using "generics" in your code.
