New Contributor
Super ContributorHi Caius,
According to your Verilog code, you are using first character for your identifier in module,port,signal assignment and statement equation with number. Either you change to new name for identifier or put ("\") if you want to keep the identifier naming. This is a escaped identifier as it allow for any printable ASCII character to be included in the name. Escaped identifiers begin with white space. The backslash (“\”) character leads off the identifier, which is then terminated with white space. The leading backslash character is not considered part of the identifier.
Thus in your program,
module \7474 (
\2CLRN ,
\2CLK ,
\2D , /* port identifer declaration put "\" */
\2PRN ,
\1CLRN ,
\1CLK ,
\1D ,
\1PRN ,
\1Q ,
\1QN ,
\2Q ,
\2QN
);
input wire \2CLRN ;
input wire \2CLK ;
input wire \2D ;
input wire \2PRN ;
input wire \1CLRN ; /* signal assingment put "\" */
input wire \1CLK ;
input wire \1D ;
input wire \1PRN ;
output wire \1Q ;
output wire \1QN ;
output wire \2Q ;
output wire \2QN ;
reg DFF_10;
reg DFF_9;
assign \1Q = DFF_9;
assign \2Q = DFF_10;
always @(posedge \2CLK or negedge \2CLRN or negedge \2PRN )
begin
if (!\2CLRN )
begin
DFF_10 <= 0;
end
else
if (!\2PRN )
begin
DFF_10 <= 1;
end
else
begin
DFF_10 <= \2D ; /* statement all identifier put "\" */
end
end
assign \2QN = ~DFF_10;
assign \1QN = ~DFF_9;
always@(posedge \1CLK or negedge \1CLRN or negedge \1PRN )
begin
if (!\1CLRN )
begin
DFF_9 <= 0;
end
else
if (!\1PRN )
begin
DFF_9 <= 1;
end
else
begin
DFF_9 <= \1D ;
end
end
endmodule
Thanks,
Regards
