Translating to Verilog and compiling Maxplus2 .bdf examples

Ok, maybe I was not being clear enough. ANYWHERE a non-standard format identifier (ie, starting with an alphabetic, and then containing only alphabetic, numeric, or underscore) is used it MUST be escaped. So in your above code, the identifiers in the module port list, in the assign statements, and those in equations in the always blocks need escaping. Here is what your code should look like:

module \7474 (
   \2CLRN ,
   \2CLK ,
   \2D ,
   \2PRN ,
   \1CLRN ,
   \1CLK ,
   \1D ,
   \1PRN ,
   \1Q ,
   \1QN ,
   \2Q ,
   \2QN 
);
 
input wire   \2CLRN ;
input wire   \2CLK ;
input wire   \2D ;
input wire   \2PRN ;
input wire   \1CLRN ;
input wire   \1CLK ;
input wire   \1D ;
input wire   \1PRN ;
output wire   \1Q ;
output wire   \1QN ;
output wire   \2Q ;
output wire   \2QN ;
 
reg   DFF_10;
reg   DFF_9;
 
assign   \1Q = DFF_9;
assign   \2Q = DFF_10;
 
always @(posedge \2CLK or negedge \2CLRN or negedge \2PRN )
begin
if (!\2CLRN )
   begin
   DFF_10 <= 0;
   end
else
if (!\2PRN )
   begin
   DFF_10 <= 1;
   end
else
   begin
   DFF_10 <= \2D ;
   end
end
 
assign   \2QN = ~DFF_10;
assign   \1QN = ~DFF_9;
 
always@(posedge \1CLK or negedge \1CLRN or negedge \1PRN )
begin
if (!\1CLRN )
   begin
   DFF_9 <= 0;
   end
else
if (!\1PRN )
   begin
   DFF_9 <= 1;
   end
else
   begin
   DFF_9 <= \1D ;
   end
end
 
endmodule