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CFabr1's avatar
CFabr1
Icon for New Contributor rankNew Contributor
5 years ago

Translating to Verilog and compiling Maxplus2 .bdf examples

Hi all, I'm trying to translate to Verilog some Maxplus2 examples (in .bdf format) of TTL gates but I get some errors when compiling.I'm using Quartus 12.1 For example, this is the generated Verilo...
ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
5 years ago

Port and signal names cannot start with a digit. The name must be escaped when used (ie, change 2CLK to \2CLK AND add a trailing space after the name).

So for example 'input wire 2CLRN;' becomes 'input wire \2CLRN ;' etc.