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Altera_Forum
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14 years ago

Transceiver Pin Assignment for Stratix 4 GX

Hi

i implemented a transceiver with the ALTGX megafunction and want to assign the pins (tx_dataout_sig[1...4]).

The I/O Standard should be 1.4V PCML. (As seen in the assignments) 


set_location_assignment IOBANK_QL1 -to tx_dataout_sig -disable
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to tx_dataout_sig -disable
set_location_assignment PIN_AD36 -to tx_dataout_sig
set_location_assignment PIN_AD37 -to "tx_dataout_sig(n)"
set_location_assignment PIN_AB36 -to tx_dataout_sig
set_location_assignment PIN_AB37 -to "tx_dataout_sig(n)"
set_location_assignment PIN_T36 -to tx_dataout_sig
set_location_assignment PIN_T37 -to "tx_dataout_sig(n)"
set_location_assignment PIN_P36 -to tx_dataout_sig
set_location_assignment PIN_P37 -to "tx_dataout_sig(n)"
set_instance_assignment -name BOARD_MODEL_TERMINATION_V "HALF VCCIO" -to tx_dataout_sig
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to tx_dataout_sig
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to "tx_dataout_sig(n)"
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to tx_dataout_sig
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to "tx_dataout_sig(n)"
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to tx_dataout_sig
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to "tx_dataout_sig(n)"
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to tx_dataout_sig
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to "tx_dataout_sig(n)"
set_instance_assignment -name BOARD_MODEL_TERMINATION_V "HALF VCCIO" -to tx_dataout_sig
set_instance_assignment -name CKN_CK_PAIR ON -from tx_dataout_sig -to "tx_dataout_sig(n)"
set_instance_assignment -name CKN_CK_PAIR ON -from tx_dataout_sig -to "tx_dataout_sig(n)"
set_instance_assignment -name CKN_CK_PAIR ON -from tx_dataout_sig -to "tx_dataout_sig(n)"
set_instance_assignment -name CKN_CK_PAIR ON -from tx_dataout_sig -to "tx_dataout_sig(n)"
But the signal displayed on my scope is only from 84mV to 212mV... So it's nothing about 1.4V PCML.

Do I have to set any other settings?

Thanks for your help!

Thomas

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi, i'm the colleague of thomas and i wrote the firmeware.

    Here are some additional information about the transceiver configuration.

    • Protocol: Basic X4

    • Transmitter only

    • Effective datarate : 1720 Mbps

    • inclk frequency : 430 MHz

    • PLL bandwith: Auto

    • VCCHTX: Auto

    • Pre-emphasis pre-tap: 0

    • Pre-emphasis first Post-tap: 0

    • Pre-emphasis second post-tap: 0

    • Self test mode: none

    • low latency PCS mode is enabled

    • No reconfiguration and loopbacks

    We use the Stratix IV signal integrity development board DK-SI-4SGX230N.

    I only want to put out a pulscode of '1010...'. The calibration clock signal is the 100 MHz clock from the development board (PIN_A34, LVDS).

    i_tx_ref_clk is connected to the transceiver clock PIN_AN38 (LVDS) and generated by a Rohde&Schwarz SMHU Signal Generator ( 430MHz, sine wave) 

    
    u_tx_channel : tx_channel
      port map
      (
        -- inputs
        cal_blk_clk            => i_tx_calibration_clk,
        cal_blk_powerdown => '0',
        pll_inclk                 => i_tx_ref_clk,
        pll_powerdown        => '0',
        tx_digitalreset        => '0',
        tx_datain               => x"AAAAAAAAAAAAAAAA",
        coreclkout(0)         => memory_clk,
        tx_clkout               => open,
        tx_dataout             => tx_dataout_sig
      );
    Now I try to connect to the transceiver via the transceiver toolkit. I load the design and clicked on "Link Instance to device ...." but nothing happened. No Transmitter Channel is displayed.