Honored ContributorHello. I am new in VHDL. I try to create train ticket machine using vhdl. It have 3 destination and all destination have fee. When user insert money with same of fee, ticket will out and no change but if user enter extra money than fee, ticket will out also with change.When i run the simulation all output does not appear. Anybody can help me with my code below,please. Thanks. God bless you.
Honored ContributorAre you simulating with Model-Sim? If yes, when you start it probably you see that it hangs. What really happens is that your testbench doesn't have a stop condition, so simulation never ends:
--- Quote Start --- wait; end process; END; --- Quote End --- If yes, you may click the STOP button or replace the last lines of testbench with assert falsereport "simulation completed"
severity failure;
end process;
end;
Honored ContributorThanks for reply. Already try the code that you mention but still does not work. Here my simulation.
Honored ContributorYou're using ISE/ISim. This is an Altera Forum.
There is something strange in your code. You control output like Retrn inside clk'event if. So Retrn is registered. But when you detect reset condition, you assign a reset value only to "Train_state". The simulator show cleary that some signals have and undefined state ( UUUU ).Honored ContributorThanks. But i still dont get it. can u show me which code that wrong and what the exactly code that i need change it.
Honored ContributorI try a little change but all my output std_logic_vector still uuu. how i can change it to make sure output uuu will not come out. Assume I am zero in VHDL code.Thanks
Honored ContributorAs I said, assign a value to the output vectors on reset conditions. I do it and Retrn vector gets a defined value. With "money_sum" vector the problem in different. You forgot this signal in the component instantiation in the testbench ( look at the original code ). When you add it, money_sum gets a defined value too.
Because some reason you declare money_sum as inout, so i place the reset value as Hi-Z ( "ZZZZ" ). Check what is the right value on this situation. I post the corrected codes.Honored ContributorOK. Here my simulation.I already tried it. I'm sorry. But, is is my code for make output appear like change, return,money_sum also ticket is correct? I mean in every single state to make output appear. Please let me know.Thanks.
Honored ContributorCan you explain in more detail how should work this circuit? I will help you better.
Honored ContributorOk. For example output that I want, if kl_station=1 which the fees for kl ticket is greater than 2.When RM1 insert, Money_sum<="0001",when RM2 insert,Money_sum<="0011" because RM1 + RM2. Then, ticket will be 1 and change must equal to "0001". I hope you understand what I mean.Thanks
Honored ContributorI don't undestand very well, but it will useful to add the state register to the waveforms. Money_sum is "0001" the after 1 clock cycle RM1 goes '1'. Probably you inferred a register for money_sum but its next state logic isn't clear in your code.
