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Altera_Forum
Honored Contributor
Honored Contributortop level block symbol map question
Hi, I have a project written in Verilog. The top level (CPU) connects several lower level components with lots of signals to connect. is there any way in quartus to make a printable diagram tha...
Altera_ForumHonored Contributor
Honored ContributorHave a look at the RTL view from netlist viewers in tools menu.
