Tools to verify radiation hardened designs in VHDL

Hey,

During my bachelor thesis I programmed two tools to verify radiation hardened designs, especially TMR Designs.

The first tool is a TCL extension for modelsim to induce SEEs during the test.

The second tool is for inducing errors in a hardware via JTAG, to verify the place and route step.

If you are interested have a look.

http://www.blog-tm.de/?p=178

I would like to hear some feedback...

best regards

Tobias