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Altera_Forum's avatar
Altera_Forum
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18 years ago

Tool for identifying resource consumption

Hi all ... I've got a project that's been built in Quartus II for a Cyclone III chip written in verilog. I'm trying to get a better handle on what's driving my LE consumption so that I ca...
Altera_Forum's avatar
Altera_Forum
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18 years ago

I guess what you need is a high-level breakdown of the logic in your design, e.g. number of operators, N:1 muxes, basic logic gates. As Rysc points out, you can browse through your design in the RTL Viewer, but the same information in a tabular format would be much more convenient. I don't think this feature exists in Quartus II, so you may want to file an enhancement request.