Honored ContributorHi,
There are two similar assignments in Quartus II, Toggle Rate and Power Toggle Rate. It seems their definitions are summerized as in the PPT file attached. Is this correct? Thanks
Honored ContributorHello,
interesting question! The document implies, that toggle_rate, a parameter that can be assigned to pins, would be evaluated in signal integrity analysis. Unfortunately, this isn't mentioned at any place neither in Quartus Handbook nor in device manuals, where pin placement rules are explained. Thus I guess, the information is either simply incorrect or is about a feature to come. However, I don't see how a toggling rate should exactly be evaluated in SSO (simultanous switching output) signal integrity rules. Regards, FrankHonored ContributorRegardless of its use for signal integrity analysis, which I think would be fairly new, the "toggle rate" setting has long been in Quartus for what gee's attachment says about checking pin-out restrictions like a toggling single-ended pin near a differential pin. An example of its use: Tell Quartus that a static single-ended pin like a board slot ID input has a toggle rate of zero. Setting toggle rate to zero lets Quartus know it may place that pin closer to a differential pin than the device handbook restrictions say is allowed for toggling single-ended pins. See http://www.altera.com/support/kdb/solutions/rd05052003_3407.html.
Honored ContributorHello Brad,
the support note is the missing link. The same was ment in the document shown by gee, I guess. I must confess, I hadn't been able to imagine a function of toggle_rate assignment, as it is revealed in the support note: Using a rate value as binary switch! But that's actually the only thinkable way to evaluate a rate in placement rules. Claim the pin isn't toggling at all, than it is ignored as a possible source of interference. (It may toggle though, but then it's your problem...). I also have heard, that there may be "backdoors" to modify pin placement rules through quartus.ini assignments. This gives also a means to solve the recently discussed Cyclone III active parallel pin mapping issue. Just declare the flash pins as static signals, at worse get some interferences when using PFL. Thank you for clarifying the point. I guess, one can find it using the keyword TOGGLE RATE in knowledge base, but why not in Quartus Handbook, why not in device manuals? Regards, Frank
