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Altera_Forum
Honored Contributor
Honored ContributorTo measure internal delays in circuits
Hi, I want to measure the internal delay of gates using FPGA hardware and compare the propagation delays of several circuits such as ripple-carry and carry-lookahead adders. I want to measure the...
Altera_ForumHonored Contributor
Honored ContributorHow about using the Quartus tools to generate a post place and route simulation netlist (ie, .vo files) and delay annotation (ie, .sdo files).
I do this as a routine part of my flow in case I need to inspect the detailed timing behavior of some portions of the design (altho not very often any more). The 'quartus_eda' tool is used to generate this netlist, and some setup in the .qsf file as well: set_global_assignment -name EDA_SIMULATION_TOOL "NC-Verilog (Verilog)" set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
