To measure internal delays in circuits

How about using the Quartus tools to generate a post place and route simulation netlist (ie, .vo files) and delay annotation (ie, .sdo files).

I do this as a routine part of my flow in case I need to inspect the detailed timing behavior of some portions of the design (altho not very often any more).

The 'quartus_eda' tool is used to generate this netlist, and some setup in the .qsf file as well:

set_global_assignment -name EDA_SIMULATION_TOOL "NC-Verilog (Verilog)"

set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation