Tips for solving routing congestion? How to debug?

There is a Routing Utilization report you can run in the Chip Planner. It allows you to show where there are areas of congestion, but it doesn't actually tell you what's in that area. You can go the Hierarchy Browser in the main Quartus window and right-click on hierarchies and locate to the Chip Planner to see where things are placed and look for an overlap.

Routing congestion is very difficult to debug because there is seldom a smoking gun. Let's say you had a reset that cause routing congestion. By itelf, it would easily route, so it's the combination of all the other logic routing with the reset that results in the no-fit.

Actually, the one smoking gun I find is when the router adds delay to meet hold requirements. This is usually caused by incorrect multicycles(a multicycle setup without a related multicycle hold) or incorrect clock constraints(paths going between unrelated clocks, which might have something like a 0ns hold requirement, but due to clock skew a lot of delay needs to be added). Look in the fitter report's Estimated Delay for Hold timing, both Summary and Detailed, and see if anything looks wrong. The other thing I do is go to More Fitter Options, set Hold Optimizations to Off, and compile, then in TimeQuest see what fails hold timing. If it's just regular paths(like paths on a global clock tree that fail by a few 100ps) that is expected, but if there are unrelated clock domains failing hold or something like that, then fix those up first and then turn hold on and recompile. (Don't forget to look at Removal timing too, which is similar to hold, where the router adds delay to fix the timing).

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How can I debug the source of my routing congestion? Quartus says that routing details can be found in the Chip Planner, but I to looked there and I couldn't understand how to use the information to find the routing issue. For example, the source of my routing congestion could be a reset signal, but how can I can be more confident in that idea before I start another compilation (it takes over 6 hours to compile my design before it gives the error message for routing congestion).

Also are there compilation settings I can adjust to help with routing? I turned on Aggressive Routing Optimization, but is there something else I should try?

Finally, will adding more registers at the I/O pins and spreading the I/O pins out across the device help with routing?

Btw, I am targeting an Arria 10 device and my design takes up approximately 80% of the logic resources.

Thanks in advance!

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I assume in many cases of routing failure the cause is to do with routing resource rather than specific path routing failure (which may also occur). Just like luts or registers you may deplete routing resource in your design. Unfortunately the fitter report does not directly show figures for routing utilisation like it does with luts ...etc.

For example your design may be having massive muxes e.g. you have 1000 nodes switched with 1000 nodes in an AND function but such that each one node from set of 1000 may AND with any one node of other set of 1000 nodes leading to 1 million routing requirement.