--- Quote Start ---
How can I debug the source of my routing congestion? Quartus says that routing details can be found in the Chip Planner, but I to looked there and I couldn't understand how to use the information to find the routing issue. For example, the source of my routing congestion could be a reset signal, but how can I can be more confident in that idea before I start another compilation (it takes over 6 hours to compile my design before it gives the error message for routing congestion).
Also are there compilation settings I can adjust to help with routing? I turned on Aggressive Routing Optimization, but is there something else I should try?
Finally, will adding more registers at the I/O pins and spreading the I/O pins out across the device help with routing?
Btw, I am targeting an Arria 10 device and my design takes up approximately 80% of the logic resources.
Thanks in advance!
--- Quote End ---
I assume in many cases of routing failure the cause is to do with routing resource rather than specific path routing failure (which may also occur). Just like luts or registers you may deplete routing resource in your design. Unfortunately the fitter report does not directly show figures for routing utilisation like it does with luts ...etc.
For example your design may be having massive muxes e.g. you have 1000 nodes switched with 1000 nodes in an AND function but such that each one node from set of 1000 may AND with any one node of other set of 1000 nodes leading to 1 million routing requirement.
Honored Contributor
