Hello, we currently experience strange timing closure problems with a design. On my local workstation it usually works, even with "balanced" settings. The same design, same settings, same assignments on our CI build system fails frequently. Even when I increase to the highest speed optimized settings it fails with a small TNS of about -0.03ns. The problem therefore seems to be related to Quartus, not the design itself. The Quartus documentation says the results should be deterministic regardless of the system provided the seed and max CPU cores setting is identical, which is the case here. This statement is obviously false here, since even a 100% identical project produces different results on both systems. The hardware differs - the workstation is a Ryzen based system, the CI uses Xeons. I already tried to set a slack margin of 1ns, without any improvement. So the questions are: 1. Why do we see different results despite the documentation states otherwise? 2. How can we achieve deterministic results in the build process? 3. How can we fix the fitter giving up at this really small margin, since it is obviously not a design related issue? Thanks!