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Altera_Forum's avatar
Altera_Forum
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15 years ago

Timing

Sorry for low quality of my question, but is a few time I work in VHDL, but I improved in progress, My question is that: I am working whith counter circuits

example quadrature encoder and others, my problems is, to synkronize the signal delayed, one clock is connected at 8 flip flop any latch have the same clock, and must be arrive at the last flip flop, whith clock at the same time of the gate output, where I can find documentation for resolve my timing problems? the Altera help, suggest to see designe documentation, but I not found, there are not the possibility to insert a small delay, before to connect the clock to any latch, somes example are not possible to find in the altera site??

thanks

Maurizio

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Maurizio,

    I don't think inserting clock delay is required for solving such a problem, nor is a good design practice, IMHO.

    From what I can understand, you have a chain of latches and each introduces a delay but I can't get your point.

    Can you explain better your problem or post the hdl code for the problem case?

    Regards

    Cris
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks for help, I attach the file complete, the file

    is not important, I use only for learnig, is not ready for

    use on any applycations, and are full of error, that is good only for

    experiments, but for me are a good point for start, to the next applycations,

    any suggestions can only improved my aknowledge.

    regards
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    This is a lot of code and I don't have time to analyze it.

    Anyway I see from your comments that you have a 4MHz system clock.

    If this is true I think it is virtually impossible not meeting the timing requirements with so a slow clock, unless you have a design error.

    From a rapid inspection all seems to be made synchronous to the main clock.

    From what you said in the original post, I suppose your problem is with the bcd counters chain: they are correctly clocked with the same signal and inserting delays is not correct. Maybe you mean you want update digit 0, then digit 1 based on digit 0 new status and so on?

    In this case I think you need major changes in the behavioral code.

    Cris