Timing

This is a lot of code and I don't have time to analyze it.

Anyway I see from your comments that you have a 4MHz system clock.

If this is true I think it is virtually impossible not meeting the timing requirements with so a slow clock, unless you have a design error.

From a rapid inspection all seems to be made synchronous to the main clock.

From what you said in the original post, I suppose your problem is with the bcd counters chain: they are correctly clocked with the same signal and inserting delays is not correct. Maybe you mean you want update digit 0, then digit 1 based on digit 0 new status and so on?

In this case I think you need major changes in the behavioral code.

Cris