Forum Discussion
Occasional ContributorTiming Violations in JTAG Signals
After internal testing and discussion, we’ve confirmed the following for Arria 10 devices:
- Only the on-board USB-Blaster II is capable of supporting up to 24 MHz.
- The off-board USB-Blaster II cannot reach 24 MHz due to certain limitations
- That said, if the TDO pin of the Arria 10 is driving the TDI of another device through a short trace, it can still support up to 24 MHz.
In the SDC files, you’ll notice a placeholder such as <<customer here>>. This needs to be updated based on the actual trace length measurements on your board. If you're targeting 24 MHz, the timing constraints will need to be tighter to meet the higher frequency requirements.
I'll attach a sample SDC file that helps close timing at higher speeds. Let me know if you have any further questions.
Super Contributor1) Can you double check if you have missing constrain by following the below:
https://www.intel.com/content/www/us/en/support/programmable/articles/000092769.html
2) Do you have signal tap added to your design? If yes, can you temporally remove the signal tap and see if there are still timing violation?
Occasional Contributor1) I did the check with the mentioned sdc template and it matches completely the design .sdc file, except for an assignment which is only valid for Stratix10. Since I'm using Aria 10 this won't be applied.
2) I don't have any signal tap in my design. The only thing I use is JTAG to Avalon Master Bridge Intel FPGA IP Version 19.1 which accesses the main Avalon system bus
best regards
Fabian
