Timing violations - TimeQuest vs. Compile results ?????

Adding multicycle should be a last resort to fixing timing issues, and, as mentioned, should only be used to describe how your design is actually supposed to work, like the divide-by-2 clock enable mentioned. You should look at the failing paths in your design, go back to your HDL code, and make adjustments there first. Adding pipelining is a relatively simple way of improving performance at the expense of extra cycles of latency. If you could post some code here that is failing timing, maybe we can help!