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Altera_Forum's avatar
Altera_Forum
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9 years ago

Timing violations - TimeQuest vs. Compile results ?????

I am pretty new to working with TimeQuest and working out timing violation in a design. In our current design we seem to be having some timing issues so I started looking at the TimeQuest analyser. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Yes, it will ease up the timing, but that is only valid if your signals behave in a multi-cycle manner. Eg. Your clock enable is high every other clock cycle - so the signals that use that enable only change once every 2 clocks, so the q output of the register is valid for 2 clock cycles - hence a multi cycle constraint.

If the registers in your design can change every single clock cycle then you do not have a valid multi-cycle constraint. If you specify one, then the design may not work properly on the board.