Timing violations - TimeQuest vs. Compile results ?????

Thank you for your quick reply

Please could you explain more by what you mean by "valid multicycle setup constraints"

It seems from what I have read that the multicycles can be used to ease up the routing of the Quartus compiler allowing better timing for the more critical signals - is that correct ?

From within Timequest for each set of violations I checked the design and the data path to see if I relax the timing requirements for the given register-to-register path, "allowing the Quartus II Fitter to place and route the design more optimally". e.g. for setup end multicycle I ensured that the latch clock could be "moved to the right" (relative to the launch clock) i.e. delay the latch clock relative to the launch clock. I checked this by verifying that if the delayed data was clocked by a latter latch clock edge the results would still be valid.