Timing violations - TimeQuest vs. Compile results ?????

Are these valid multicycle setup constraints? Or are you just using them to fix timing? You can only use multicycle constraints when you know a signal will be set for longer than a single clock period. eg. you have a system with a periodic clock enables - you can put multicycle constraints on all of the registers that use the enable (but not the enable signal itself).

Timing problems are primarily a problem with your design, not your timing specs. Have you thought about increasing pipelining in the design? Setup violations occur when registers have too much logic between them.