Forum Discussion

MRenn's avatar
MRenn
Icon for New Contributor rankNew Contributor
6 years ago

Timing violation with Altera GPIO in DDR mode

I have a setup violation at the register after the input register. The input register is constrained as described in AN433. set_input_delay -add_delay -clock virt_adc_clk -min -0.6 [get...
MRenn's avatar
MRenn
Icon for New Contributor rankNew Contributor
6 years ago
do I have to use an IO PLL to create the reference clock of 131.072MHz

I connected the 262.144MHz clock to the strobe input and to an IO PPL the create the 131.072MHz reference clock. There is still something wrong.

Thanks.

H