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MRenn's avatar
MRenn
Icon for New Contributor rankNew Contributor
7 years ago

Timing violation with Altera GPIO in DDR mode

I have a setup violation at the register after the input register. The input register is constrained as described in AN433. set_input_delay -add_delay -clock virt_adc_clk -min -0.6 [get...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

You may connect the 262.144MHz clock to the strobe. The reference clock signal is the reference clock for the PLL where you may set the frequency in the IP Parameter Editor.

Thanks.