Forum Discussion

MRenn's avatar
MRenn
Icon for New Contributor rankNew Contributor
7 years ago

Timing violation with Altera GPIO in DDR mode

I have a setup violation at the register after the input register. The input register is constrained as described in AN433. set_input_delay -add_delay -clock virt_adc_clk -min -0.6 [get...
MRenn's avatar
MRenn
Icon for New Contributor rankNew Contributor
7 years ago

Hi,

it doesn't fit. I don't know how set up the reference clock.

In AN756 it looks like I need a strobe and a reference clock, but I have only the ADC Clock with 262.144MHz.

Thanks.

​