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New Contributor

6 years ago

Timing violation with Altera GPIO in DDR mode

I have a setup violation at the register after the input register. The input register is constrained as described in AN433. set_input_delay -add_delay -clock virt_adc_clk -min -0.6 [get...

KhaiChein_Y_Intel

Regular Contributor

6 years ago

Hi,

I am sorry for the late reply as I was out of office for 5 days.

The I/O standard you are using is 1.8V. According to the User guide, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pdf, user has to use terminated I/O standards if the GPIO is operating at a frequency higher than 250 MHz. SSTL, HSTL, POD and HSUL I/O standards are terminated I/O standards.

Thanks.

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Timing violation with Altera GPIO in DDR mode

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