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MRenn's avatar
MRenn
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6 years ago

Timing violation with Altera GPIO in DDR mode

I have a setup violation at the register after the input register. The input register is constrained as described in AN433. set_input_delay -add_delay -clock virt_adc_clk -min -0.6 [get...
MRenn's avatar
MRenn
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6 years ago

Hi,

I tried with Input Delay 0, 1 and 63.

With more delay the setup slack is higher. With Delay set to 1 the hold slack is positive.

I also tried with FAST_INPUT_REGISTER on. No difference.

I never got less than -0.962ns setup slack.

The data delay is 1.341ns. Is the the correct value for a register located within the I/O?

Thanks