Timing violation while integrating 2 display port example designs

Hi Paul,

Apologize for the delayed response as there is some technical difficulty.

I have reviewed the design you shared here.

After further discussion, I found that there are a lot of clocks unconstrained and require to add sdc for these clocks.

Quartus Screenshot

Our internal team has modified the dp.sdc file and the timing result looks ok.

You may copy the dp.sdc file attached here and replace in your "\\designfile\fpga_top_intg_22_2_0_94(1)_restored\golden\golden_reset_sync_folder_structured\mySDC" directory, then re-compile the design.

Hope this answers your question.

Thank you.

Best Regards,

ZulsyafiqH_Intel