Timing simulation looks same as functional simulation in Quartus Introduction tutorial

I'm trying to follow the Quartus Introduction tutorial from https://fpgauniversity.intel.com/redirect/materials?id=/pub/Intel_Material/14.1/Tutorials/Verilog/Quartus_II_Introduction.pdf. This is just a simple XOR.

However, at the step where I run timing simulation, I do not see any delay in the waveform as the tutorial shows. Instead, it looks identical to what I see in functional simulation.

What am I missing? I'm using Quartus Prime Lite edition 18.1.0 Build 625. I've configured Assignments -> Settings -> Simulation to use Modelsim-Altera. I also noticed that after compilation, 'Timing Analyzer' is red and warns about unconstrained paths, so perhaps I'm missing something here?