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Altera_Forum
Honored Contributor
Honored ContributorTiming Simulation and altsyncram
Hi, I'm currently developing a project using the schematic design in Quartus 13.0. There, I have included 4 memory blocks using the RAM (megafunction). It seems that I have a problem with 2 of ...
Altera_ForumHonored Contributor
Honored ContributorWithout seeing the design, we have little idea as to what the problem is
