Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Timing Simulation and altsyncram

Hi, I'm currently developing a project using the schematic design in Quartus 13.0. There, I have included 4 memory blocks using the RAM (megafunction). It seems that I have a problem with 2 of ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Without seeing the design, we have little idea as to what the problem is