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Altera_Forum's avatar
Altera_Forum
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11 years ago

Timing requirement not met.

Hi! I'm new to FPGA. Recently, I compiled an licensed IP designed to be worked on Cyclone SOC V. The Quartus II I installed is 13.1 64-bit web edition for Linux. After the compilation done...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Without being an expert I would advice you to check on the Fitter settings. Perhaps the vendor's setup has different fitter settings causing his design to be fitted differently causing different timing. You could ask your vendor to provide you with his list of Fitter and/or Analysis&Synthesis settings.