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Altera_Forum's avatar
Altera_Forum
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14 years ago

Timing problems moving from sopc_builder to Qsys

I've just converted an sopc_builder system to a qsys system in quartus 11.0.

The conversion went reasonably well, and I like the new qsys interface, but I'm having some serious problems closing timing in the new system.

The sopc_builder version of my design takes up 75% of my part's resources (29748/39600 LE on a EP3C40). Worst case slack is 0.328ns on my 100MHz clock.

The qsys design takes up 79% of the device (31387/39600 LE), and worst case slack is -4.117ns.

I'm moderately concerned about the size increase, but it's the timing that I'm really worried about.

The worst timing failures are between my Nios II processor and an internal RAM block that's connected using a tightly coupled data master.

Is this expected when moving from sopc_builder to qsys? Any suggestions on where to start poking to get back my performance?

Thanks,

Steve

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    How are others doing converting from sopc builder to qsys? Any obvious difference in performance or size of the resulting system?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I wouldn't expect a tightly coupled connection to suddenly become the critical timing path moving from SOPCB to Qsys. I suspect the fitter is struggling on different paths and trading off some slack in other places like the tightly coupled connection. Have you constrained all your I/O using .sdc constraints? Also are you seeing only setup timing violations or are there others in your design as well?

    If you haven't tried yet there is a pipelining setting called "Limit interconnect pipeline stages to:" on the project settings tab in Qsys. If it's set low (like 0 or 1) perhaps try increasing it to see if that makes a difference for your design.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Did you try to increase the allowed number of pipelines stages on the project settings tab of qsys? I think it is default set to 0 and i needed to increase it to 1.

    I think that they put this here to tweak performance of the system.

    regards
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Also, regarding the allowed number of pipeline stages, I would try several values, as adding pipeline stages might even lower the LE count (don't ask me how, I just saw it in their Qsys migration video). The good thing is that it will probably eliminate all timing problems (one of the reasons that I want to make the transition to Qsys), so as others suggested, try it out.